1. Sequential vs. Concurrent Statements in VHDL

architecture CONCURRENT of MULTIPLE is

   signal Z, A, B, C, D : std_logic;
begin
      Z <= A and B;
      Z <= C and D; // two and-gates, one driver
end CONCURRENT;
 

architecture SEQUENTIAL of MULTIPLE is
   signal Z, A, B, C, D : std_logic;
begin
   process (A, B, C, D)
   begin
      Z <= A and B;
      Z <= C and D; // one and-gate, no driver
   end process; // Z changes value after process suspends
end SEQUENTIAL;

2. For Loop

entity EX is
port (A : in std_logic_vector(0 to 15);
      SEL : in integer range 0 to 15;
      Z   : out std_logic);
end EX;

architecture RTL of EX is
begin
   WHAT: process (A, SEL)
   begin
      for I in 0 to 15 loop
         if SEL = I then
            Z <= A(I);
         end if;
      end loop;
   end process WHAT;
end RTL;

There are 16 comparators and 16 and-gates.

3. Wait statement

wait for <specific time>;

STIMULUS: process
begin
   SEL <= '0';
   BUS_B <= "0000";
   BUS_A <= "1111";
   wait for 10 ns;  // recalling the process after 10ns
   SEL <= '1';
   wait for 10 ns;
   -- etc, etc
end process STIMULUS;

wait on <signal list>;

process
begin
   if (A='1' or B='1') then
      Z <= '1';
   else
      Z <= '0';
   end if;
   wait on A, B; // wait on the events
end process;

wait until <condition>;

process
begin
   wait until CLK='1'; // wait until condition
   Q <= D;
end process;

wait;

STIMULUS: process
begin
   SEL <= '0';
   BUS_B <= "0000";
   BUS_A <= "1111";
   wait for 10 ns;
   SEL <= '1';
   wait; // suspends forever
end process STIMULUS;

4. PROCESSES

clocked process
entity FLOP is
  port (D, CLK : in std_logic;
      Q     : out std_logic);
end FLOP;

architecture A of FLOP is
begin
  process // no senstivity list
  begin
    wait until CLK'event and CLK='1'; // with one wait event statement
    Q <= D;
  end process;
end A;
 
Combinational Process
process (A,B) // with sensitivity list
begin
   X <= '0'; // eliminates transparent latches
   Y <= '1';
   if CONDITION then
      X <= A;
      Y <= B;
   end if;
end process;

process (A,B) // process with sensitivity list
begin
   if (A='1' or B='1') then
      Z <= '1';
   else
      Z <= '0';
   end if;
end process;

process
begin
   if (A='1' or B='1') then
      Z <= '1';
   else
      Z <= '0';
   end if;
   wait on A, B; // process with wait statement
end process;
 

process (A, B, C)
   variable M, N : integer;
begin
   M := A;  // initializes variables
   N := B;
   Z <= M + N;
   M := C;
   Y <= M + N;
end process;

2 registers in the above example
 

process (A)
   variable TMP : std_logic;
begin
   TMP := '0';
   for I in A'low to A'high loop // I needn't be declared
      TMP := TMP xor A(I);
   end loop;
   ODD <= TMP;
end process;

No limiting in the width of A
# of xor equals to width of A

 
 
5. Variables VS.. Signals
 
 

signal A, B, C, D,Y, Z : integer;
begin
   process
     variable M, N          : integer;  // declares variables here
   begin
      wait until clock'event and clock = '0';
      M := A;
      N := B;
      Z <= M + N;
      M := C;
      N := D;
      Y <= M + N;
   end process;

Eventually the values are:
Z = A+B
Y= C+D
How many registers in here? Answer: 1

signal A, B, C, D, X, Y, Z : integer;
signal M, N          : integer;
begin
   process (A, B, C, M, n)
   begin
      M <= A;
      N <=  B;
      X <= M + N;
      N <=  C;
      Z <= M + N;
      M <= C;
      N <=  D;
      Y <= M + N;
   end process;

Eventually the values are:
X = A+B
Z = A+C
Y= C+D
(Totally wrong!! Why??)
How many registers in here? Answer: 1

signal A, B, C, D, X, Y, Z : integer;
signal M, N          : integer;
begin
   process (A, B, C, M, n)
   begin
      M <= A;
      N <=  B;
      X <= M + N;
      M <=  C;
      N <=   D;
      Y <= M + N;
      Z <= X + Y;
   end process;

Eventually the values are:
X = A+B
Z = A+B+C+D
Y= C+ D
(Totally wrong!! Why??)
How many registers in here? Answer: 2

6. Operator Overloading

7. Stand_logic_arith VS. Numeric_std

8. Synthesis Issues

if SEL = '1' then
    Z <= A + B;
else
    Z <= A + C;
end if;

one or two adders?

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Last Modified: Tuesday, September 17, 2002 10:51:06 AM